`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:07:11 11/19/2020 
// Design Name: 
// Module Name:    alu 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
include "defines.v";

module ALU(
    input [31:0] a1,
    input [31:0] a2,
    input [4:0] aluOp,
    output [31:0] aluResult
    );
	reg [31:0]temp;
	integer i;
	always @*
	begin
		temp = 0; 
		case (aluOp)
			`ADDU:
				temp = $signed(a1) + $signed(a2);
			`SUBU:
				temp = $signed(a1) - $signed(a2);
			`OR:
				temp = a1 | a2;
			default:
				temp = 0;
		endcase
	end
	assign aluResult = temp;
	
endmodule
